CPU roadmap: server processors

Alan Stevens ZDNet.co.uk

Published: 16 Jun 2008

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In the Intel corner...
Keeping tabs on all the different Xeon and Itanium processors that Intel keeps pushing out to the server and HPC (High Performance Computing) markets is far from easy, but here goes.

At the time of writing (June 2008), Intel leads with its well-established family of Xeon server processors all now based on the Core micro-architecture, first introduced in 2006. Single-, dual- and quad-core products are readily available and can be broadly divided into three families: the Xeon Processor 3000 series for use in single-socket servers, the Xeon Processor 5000 series for 2-way systems and the Xeon Processor 7000 series for 4-way multi-processing and beyond.

All of the Xeons support Intel's virtualisation technology (Intel VT) and most of the current crop have been moved to Intel's 45-nanometre (nm) Hi-k metal gate silicon technology, which is the key component of the Penryn platform, enabling more cache to be put on each chip and other processing enhancements to be implemented. The latest to be ported is the Xeon 5400 series (launched in November 2007), comprising a family of quad-core processors for dual-processor (DP) systems available in both high and low energy (80W) implementations.

For high-end 4-way servers, Intel is currently shipping quad-core Xeon Processor 7300 series (Tigerton) chips based on the older 65nm technology. Tigerton is part of Intel's Caneland platform (launched September 2007) which includes a new chipset (Clarksboro) to enable it to support up to four quad-core processors — effectively giving up to 16-way SMP. It also incorporates a new point-to-point interface, giving each processor access to the full front-side bus bandwidth (1066MHz).

In the second half of 2008, Intel is expected to release a 45nm implementation of the Xeon 7000 Series processor, called Dunnington, which will simply plug into Caneland motherboards. This is now expected to be a 6-core rather than a quad-core chip, made up of 3 dual-core pairs on the same die with 3MB L2 and 16MB of L3 cache per pair. By upgrading to Dunnington, customers will effectively power up from 16- to 24-way SMP.

The forthcoming Dunnington CPU is designed for multi-processor Caneland servers: a four-way system with this 45nm processor will have 24 cores.

Further down the line (early 2009) Intel is set to introduce a totally new NUMA-based architecture that's designed to be a lot more scalable than Intel Core, enabling it to further increase the number of cores per chip (up to 16 or more) as well as help minimise power and cooling requirements. Known as Nehalem, the new architecture offers greater parallelism and enhanced multi-threading support. It will also incorporate a dedicated point-to-point interconnect (QuickPath) to link processors to each other and directly to memory — much like AMD's HyperTransport. An integrated DDR3 memory controller will also be included with three memory channels per processor.

By 2010 Nehalem processors are set to be shrunk even further onto 32nm dies (Westmere) after which, in accordance with the Intel's 'tick-tock' development cycle, the company is planning to introduce yet another architecture revamp (Sandy Bridge); among other enhancements, this will improve floating-point performance by incorporating Intel's 256-bit Advanced Vector Extension (AVX) technology.

Intel's 'Tick-Tock' development cycle in action: 45nm Nehalem architecture chips will shrink to 32nm ('tick') and then be superseded by the Sandy Bridge architecture ('tock').

Lastly, the ill-fated Itanium hasn't gone away. Officially now the Intel Itanium 9000 series, it too has been revamped with the latest Montvale implementation — a 90nm product available in both single- and dual-core formats. Montvale offers support for higher clock speeds than its predecessor (the Montecito) plus a faster frontside bus and low power requirements, and is designed for use on highly scalable SMP systems with up to 2,048 processors. A move to 65nm (Tukwila) is expected in 2009 with a 32nm implementation (Poulson) to follow.

 

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