Inside Intel's Atom

Rupert Goodwins ZDNet.co.uk

Published: 03 Jun 2008

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Enter the Atom
And now the Atom, Intel's smallest processor. At under 25 square millimetres, it's a tenth the area of a Pentium 4 chip while having 47 million transistors compared to the P4's 42 million. A lot of that comes from the Atom being a 45nm chip, opposed to the P4's 180nm, but there are also a number of design efficiencies.

Intel's 45nm Atom processor occupies just 25 square millimetres — a tenth the size of the 180nm Pentium 4.

The Atom is a two-issue processor, meaning it can cope with two instructions simultaneously, as opposed to the more common three- and four-issue designs. Furthermore, it fully inspects each instruction before deciding what to do with it; other processors make assumptions and take the hit of redoing things if the guess was wrong. That turns out to be power-inefficient, especially with long pipeline architectures where the processor has lots of different instructions going through different stages of digestion: the need to go back and start again means an awful lot of joules that should have been spent on getting an answer are merely thrown away when the pipeline reloads.

The Atom architecture is a two-issue design with a 16-stage pipeline.

The Atom processor die.

Although the Atom's pipeline is longer than the Core 2 Duo's — 16 instead of 13 stages — each stage is rather simple. This has allowed the designers to concentrate on optimising for power consumption in a way that's far more difficult when dealing with significantly more complex circuitry as a single block, while letting each stage run efficiently at a high clock frequency.

One of the ways it keeps that pipeline efficiently fed is by treating the three phases of many x86 instructions — which typically get data, operate on it then store it away again — as a single entity to be passed down the pipeline, instead of splitting them into three separate micro-operations. Although there are plenty of complex operations that can't be handled by this model, Intel says that around 96 per cent can be passed through the pipeline as single chunks, with a good increase in efficiency.

The instruction decoders can also pair up instructions either from the same thread or from two different threads to dispatch simultaneously: this is the return of HyperThreading (HT) — an action which, Intel claims, can provide a 30 per cent speed boost for a 15 per cent power usage increase.

Intel's very low quoted idle power figures of a hundred or so milliwatts depend heavily on the chip's C6 sleep function. This is similar to that implemented in Penryn: the chip has a split power supply with one dedicated to keeping a special area of memory alive. This holds the complete chip state while the rest of the circuitry is effectively turned off — in reality, held at a very low voltage, to minimise the switch-on surge — and restores that state when the chip needs to wake up again. This is fine when the chip is idling, waiting for keyboard input or some other rare event, but the mechanism is unlikely to be invoked often when the chip is busy.

Other aspects of the design also have more effect on power consumption than might be apparent. The Atom is built out of collection of over 200 predefined circuit modules (called Functional Unit Blocks), that are designed and tested independently of the whole. One of the attributes of a FUB is that its clock and power can be independently controlled, giving the chip a very high degree of finesse when balancing performance versus power consumption.

The frontside bus (FSB) on the Atom can be configured at manufacture in one of two modes, GTL — the standard signalling technology used by existing chipsets — and a new CMOS bus that uses 2.5 times less power. The I/O chip legacy is stronger in Poulsbo, the support chip that together with the Atom makes up the Menlow platform (now called Centrino Atom). Poulsbo is a collation of various different operational units on a 130nm process. It brings together Intel's own 2D video controller, memory controller, PCIe, USB and so on — but the largest unit on the chip is a 3D GPU from Imagination Technologies, who own the PowerVR architecture. The chip is very much in the old school of I/O controllers, and it won't be until the Moorestown platform in 2010 that ten times greater power savings are expected through further integration.

Moorestown is expected to add a memory controller, video encode/decode and graphics to the main CPU — Lincroft — with disk and other I/O in the Langwell chipset, and a dedicated power management circuit looking after everything.

Until then, the Atom chip will continue to be considerably more energy-hungry than its ARM competition, which now includes the Tegra chip from Nvidia, albeit less so than devices like Via's C7 and Nano. The question is whether x86 compatibility, which gives mobile devices access to many more options in operating systems, applications and drivers, is more important than battery life or performance. Intel is betting strongly that it is — and that has a power all its own.

 

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