Processors Toolkit

Photos: Intel's Silverthorne, Tukwila

Rupert Goodwins ZDNet.co.uk

Published: 05 Feb 2008 16:28 GMT

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Block diagram: Silverthorne

Silverthorne reduces power consumption by transistor design, by aggressively turning down or off unused parts of the chip, and by adjusting its working parameters according to load. Its Level 1 (L1) cache is designed to alleviate and detect soft errors, while the L2 cache has slower but more effective error detection and correction.

Photo credit: Intel

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